Conventional solid state memories employ microelectronic circuit elements for each memory bit. Since one or more electronic circuit elements are required for each memory bit (e.g., one to four transistors per bit), these devices can consume considerable chip “real estate” to store a bit of information, which limits the density of a memory chip. The primary memory element in these devices is typically a floating gate field effect transistor device that holds a charge on the gate of field effect transistor to store each memory bit. Typical memory applications include dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read only memory (EPROM), and electrically erasable programmable read only memory (EEPROM).
A different type of solid state memory commonly known as a phase-change memory uses a phase-change material as the data storage mechanism and offers significant advantages in both cost and performance over conventional memories based on charge storage. Phase change memories use phase change materials—in other words, materials that can be electrically switched between two or more phases having different electrical characteristics such as resistance. One type of memory element, for example, uses a phase change material that can be electrically switched between a generally amorphous phase and a generally crystalline local order, or between different detectable phases of local order across the entire spectrum between completely amorphous and completely crystalline phases.
The phase-change memory can be written to, and read from, by applying current pulses that have the appropriate magnitude and duration and that cause the needed voltages across and current through the volume of phase-change material. A selected cell in a phase-change memory can be programmed into a selected state by raising a cell voltage and a cell current for the selected cell to programming threshold levels that are characteristic of the phase-change material. The voltage and current are then typically lowered to quiescent levels (e.g. essentially zero voltage and current) that are below the programming threshold levels of the phase-change material. This process can be performed by the application of, for example, a reset pulse and a set pulse which can program the cell into two different logic states. In both of these pulses, the cell voltage and cell current are caused to rise at least as high as certain threshold voltage and current levels needed to program the cell.
Next, to read the programmed cell, a read pulse can be applied to measure the relative resistance of the cell material, without changing its phase. Thus, the read pulse typically provides a much smaller magnitude of cell current and cell voltage than either the reset pulse or the set pulse.
A type of phase change memory is the so-called seek-scan probe (SSP) memory which may use a cantilevered probe to read and write to a phase change storage media. In particular, a vertically and laterally actuatable cantilever may be used for SSP memory storage applications. The MEMS mechanical cantilever can be a form of a see-saw like structure with torsional beam acting as pivot for rotational actuation when a voltage is applied on an bottom electrode location under the see-saw cantilever. In order to perform electrical data Read/Write through the cantilever tip with storage media, conductor traces are needed to be connected to cantilever tip and the structure IO pads. Metal traces can usually be fully attached cantilever structure with dielectric in between to obtain full IO trace support.
However, such metal R/W trace on cantilever structure can cause series of issues. First, metal traces on cantilever torsional or in parallel above tosional beam can cause significant actuation change due to R/W trace stress and structure rigidity. Second, metal trace on the cantilever can cause significant cantilever deformation and bending due to stress bimorph effect between metal and cantilever. In addition, metal traces on electrically grounded cantilever are expected to have large parasitic capacitance coupling, which degrades the data reading sensitivity.